Systems on Chip (SOCs) typically integrate a large and diverse number of components, or core processing units, that have different performance, power, interface and connectivity characteristics. Accordingly, SOC implementations manage the complexity of multiple (and independent) clock domains, power domains and inter-component routing. Components that were previously discrete and accessible because they were part of a printed circuit board (PCB) are now “buried” deep within an SOC and are not accessible to debugging tools, such as oscilloscopes, logic analyzers and data recorders.
Debug and Power/Performance profiling of an SOC is extremely challenging as visibility into the functionality and interaction of different core processing units of an SOC is limited. Design for Debug (DFD) features are utilized to access key functionalities of core processing units of an SOC, such as internal micro-architectural states, Finite State Machine (FSM) states, low-power controls, queue status, etc. DFD features can, however, add significant complexity in routing and timing closure, area and/or performance penalty in order to instrument the design, and transport and observe debug information of an SOC.